A synchronous memory as represented by a synchronous DRAM (Synchronous Dynamic Random Access Memory) is widely used for a main memory of a personal computer or the like. The synchronous memory inputs and outputs data synchronously with a clock signal supplied from a memory controller. Therefore, a data transfer rate can be increased by using a higher clock.
However, in the synchronous DRAM, because a DRAM core steadily carries out an analog operation, an extremely weak charge needs to be amplified using a sense operation. Accordingly, a time from when a read command is issued until when the first data is output cannot be shortened. The first data is output synchronously with an external clock after a lapse of a predetermined delay time since the read command is issued.
This delay time is generally called “CAS latency”, and is set to an integer times a clock cycle. For example, when the CAS latency is five (CL=5), the first data is output synchronously with the external clock after five cycles, after fetching the read command synchronously with the external clock. In other words, the first data is output after five clocks. A counter that counts these latencies is called “latency counter”.
A circuit as described in Ho Young Song and 15 others, “A 1.2 Gb/s/pin Double Data Rate SDRAM with On-Die-Termination”, ISSCC 2003/SESSION 17/SRAM AND DRAM/PAPER 17.8, (United States), IEEE, 2003, p. 314 is known as the latency counter. The latency counter described in this paper includes plural latch circuits that latch read commands, a switch that reads a read command from any one of the latch circuits, a first ring counter that selects a latch circuit of latching the read command by sequentially circulating the latch circuits, and a second ring counter that selects a latch circuit of reading the read command by sequentially circulating the latch circuits. With this arrangement, the latched read command can be output at a timing corresponding to a difference between a count value of the first ring counter and a count value of the second ring counter.
However, because the different ring counters are used for the input and for the output, the operations of the two ring counters cannot be easily synchronized when the frequency of the clock becomes high. It sometimes becomes impossible to simultaneously reset the two ring counters at the reset time. Therefore, the count values of the latencies are deviated, resulting in a malfunction.